Field of the Invention
The invention relates to an apparatus and a method for detecting and assessing a spatially discrete dot pattern disposed in a multidimensional coordinate system, in which each dot in the pattern assumes at least two differentiatable status values. In particular, the invention relates to an apparatus and a method for recognizing and classifying a binary failure pattern of defective memory cells of a semiconductor memory.
The failure pattern of the memory cells of defective semiconductor memories provide clues to the technological problems that cause failures in the manufacture of semiconductor memories. Along with the purely statistical distribution of the failure patterns on a wafer, which as a rule is an indication of particle problems in certain chip production processes, non-statistical distributions of the failure patterns on a wafer in particular, after evaluation, provide suitable clues to systematic technological and process problems. In order to allow sufficiently statistically well-founded conclusions to be drawn about such problems, it is necessary that the failure patterns of individual semiconductor chips or distributions of the failure patterns over an entire silicon wafer be recognized and classified. One difficulty, among others, in that respect is that failure patterns can occur in the most variant and ever-changing forms. Moreover, the amounts of raw data obtained by chip testing systems and used as a basis for analysis are enormous. In a dynamic semiconductor memory chip with a memory size of 4 megs, for instance, if failed pure "0" cells, pure "1" cells and performing an OR operation on "0"-and-"1" cells are taken into account, the amount of raw data in the least favorable case is 4 megabits.multidot.3=12 megabits. As a result, the number of theoretically conceivable variants of failure patterns for a 4-megabit memory is 2.sup.4194301 -1, which is a number with approximately 1.2 million digits. An attempt is made to organize that nearly infinitely large number of failure patterns with the aid of so-called bitmaps, which represent patterns of nonfunctioning memory cells. Although a classification system with about 80 to 100 failure classes is feasible because of the similarity of the bitmaps that are obtained, nevertheless in manual assessment by a human operator, visual error analysis of all of the failure patterns of a typical wafer which is 6 inches in diameter takes about 15 hours. The attempt has been made to automate the analysis of the failure patterns with conventional methods by using a computer. However, the results prove to be unsatisfactory in the extreme, since on one hand important error classes of failure patterns are not caught by the computer and require manual reprocessing by a skilled professional, and on the other hand the analysis times in the previous methods, even using the most modern computer equipment with high computation speeds, are still too long. Thus it is hardly practicable, for relatively large semiconductor memories with a capacity of 4 megs and more, to use the analysis methods employed heretofore. In the methods used until now, because of the long computation time needed to analyze memory chip failure patterns, only samples of individual wafers or memory chip modules were taken from ongoing production and measured separately by using a special analysis program. After preprocessing of the data in a data memory especially intended for that purpose ("fail memory") in the measuring apparatus, the preprocessed data were transmitted as a raw data file from the measuring apparatus to a computer and there subjected to a primary analysis performed with a conventional programming technique. Another major disadvantage of that kind of procedure was that upon a transition to a new generation of memories, considerable portions of the preanalysis and primary analysis had to be reprogrammed. New types of failure patterns to be analyzed also had to be newly programmed, at great effort and expense.